In general, LSI (semi-conductor large-scale integrated circuit) for processing image data of digital cameras is equipped with an image processing circuit (data processing circuit) for processing entered image data.
In the image processing circuit, a line buffer is often used for holding one line of image data in the horizontal direction during raster scanning and when pixels in the vertical direction are used for data processing.
For instance, Japanese Unexamined Patent Publication No. 2009-246488 discloses a technique of a line buffer, which is provided with a single port memory for storing one line of image data, and is capable of performing a reading operation and a writing operation substantially at the same rate as the line buffer having the dual port memory.
Many of the line buffers are mounted with SRAM (Static Random Access Memory), but some of them are provided with flip-flop circuits from the standpoint of a circuit area in the case where a horizontal size of an image is short.
Generally, when the flip-flop circuits are mounted on the line buffer, the circuit configuration is broadly divided into an address system and FIFO (First-In First-Out) system.
FIG. 1 is a block diagram of the line buffer having 160 pixels on one line, implemented in the address system.
In the line buffer shown in FIG. 1, a reference numeral 11 denotes flip-flop circuits 11 for storing entered image data and prepared for 160 pixels.
Further, in the line buffer shown in FIG. 1, a reference numeral 12 denotes a write-address decoder for designating based on an entered write address, one of the flip-flop circuits 11, in which the image data is to be recorded, a reference numeral 13 denotes clock gating cells for controlling a clock supply to the flip-flop circuit designated by the write-address decoder 12, a reference numeral 14 denotes a read-address decoder for designating based on an entered read address, one of the flip-flop circuits 11 which records a pixel to be subjected to image processing, and a reference numeral 15 denotes a selector for selecting an output signal from the flip-flop circuit 11 designated by the read-address decoder 14.
In the line buffer of the address system, the flip-flop circuits 11 are assigned with addresses for storing 160 pieces of data, respectively, that is, the flip-flop circuits 11 are assigned with the addresses, for example, from 000 to 159 for storing 160 pieces of data beginning from the leading data.
In the case where the image data is recorded in the flip-flop circuit (FF000) having the address 000, when an address of 000 is designated as the write address, then the write-address decoder 12 brings the clock gating cell (CG000) 13 for supplying a clock to the flip-flop circuit (FF000) in the selected state and keeps the other clock gating cells 13 out of the selected state, whereby the image data is written to the flip-flop circuit (FF000) having the address 000.
On the contrary, in the case where the image data is read from the flip-flop circuits 11, for example, when an address of 000 is designated as the read address, then the read-address decoder 14 controls the selector 15 so as to output the image data written in the flip-flop circuit (FF000) having the address 000.
The line buffer of the address system is a circuit, which executes substantially the same operation as SRAM, which records the image data in the flip-flop circuit designated by use of the write address, and reads the image data from the flip-flop circuit designated by used of the read address.
FIG. 2 is a block diagram of the line buffer having 160 pixels on one line similar to as shown in FIG. 1, implemented in FIFO system.
In the line buffer of FIFO system shown in FIG. 2, a reference numeral 21 denotes a flop-flop block for storing entered image data, consisting of sequentially connected shift registers for storing 160 pixels.
In the line buffer of FIFO system shown in FIG. 2, a reference numeral 22 denotes a clock gating cell, which controls a clock supply to the whole flip-flop block 21, when data in the flip-flop block 21 consisting of the shift registers is shifted, and a reference numeral 23 denotes FIFO controlling unit for controlling shifting operation of the flip-flop block 21.
In the line buffer of FIFO system, in the case where image data of 160 pixels is stored in the line buffer, the image data of 160 pixels is sequentially entered from the leading pixel to the flip-flop block 21. The FIFO controlling unit 23 controls the clock gating cell 22 so as to supply a clock to the flip-flop block 21. When the clock is supplied to the whole flip-flop block 21 from the clock gating cell 22, then the flip-flop block 21 performs the shifting operation, whereby the image data of 160 pixels is stored in the flip-flop block 21.
In the case where image data is read from the flip-flop block 21, the FIFO controlling unit 23 controls the clock gating cell 22 so as to supply a clock to the flip-flop block 21. When the clock is supplied to the whole flip-flop block 21 from the clock gating cell 22, then the flip-flop block 21 performs the shifting operation, whereby the image data entered first is read first and thereafter the image data of 160 pixels is successively read from the flip-flop block 21.